Half Adder and Full Adder: GCSE Computing Logic Circuits Explained

Logic gates are the building blocks of computer hardware, and when you wire two of them together you can add binary digits. A half adder combines an XOR gate and an AND gate to produce a sum bit and a carry bit — the tiniest slice of the arithmetic logic unit made visible.

Why do we need special circuits for binary addition?

Adding binary digits follows simple rules — 0+0=0, 0+1=1, 1+0=1, and 1+1=10 (zero, carry one). The last case is the interesting one: the result cannot be expressed in a single bit, so it generates a carry that must flow into the next column, exactly like carrying a ten in decimal long addition.

Binary addition within the CPU's arithmetic logic unit (ALU) is performed by chains of logic gate circuits. Understanding how a half adder works reveals the connection between the abstract Boolean logic you study and the physical transistors that perform arithmetic billions of times per second.

What is a half adder?

A half adder adds two single-bit inputs — call them A and B — and produces two outputs:

• Sum (S): the result bit for that column
• Carry (C_out): the carry bit passed to the next column

The logic is straightforward:

• Sum is 1 when A and B are different (exactly one of them is 1) → XOR gate
• Carry is 1 only when both A and B are 1 → AND gate

Half adder truth table:

Gate equations:

S = A XOR B
C = A AND B

The half adder is called "half" because it cannot handle an incoming carry bit — it only adds two fresh inputs. That is where the full adder comes in.

What is a full adder?

A full adder adds three inputs: two data bits (A and B) and an incoming carry bit (C_in) from the previous column. It produces the same two outputs — Sum and Carry out (C_out).

You can build a full adder from two half adders and one OR gate:

1. Half Adder 1 adds A and B → partial Sum (S1) and partial Carry (C1)
2. Half Adder 2 adds S1 and C_in → final Sum (S) and partial Carry (C2)
3. OR gate combines C1 and C2 → final C_out

Full adder truth table:

Check the last row: 1 + 1 + 1 = 11 in binary, so Sum = 1, Carry = 1. ✓

How does a worked binary addition use full adders?

To add two 4-bit numbers — say 0110 (6) + 0011 (3) — you need four full adders chained in series, with the C_out of each feeding the C_in of the next:

Column:     3    2    1    0   (right to left)
A:          0    1    1    0
B:          0    0    1    1
C_in:       0    0    1    0   (carries from right)
           ---  ---  ---  ---
Sum:        1    0    0    1   = 1001 (9 in decimal ✓)
C_out:      0    0    0    1   (carry flows left)

This chain of full adders is called a ripple-carry adder because the carry "ripples" from the least-significant bit to the most-significant bit, just like a carry propagates column by column in decimal long addition.

How does the adder link to the ALU and the CPU?

The Arithmetic Logic Unit (ALU) is the part of the CPU that performs arithmetic (addition, subtraction, multiplication) and logical operations (AND, OR, NOT). At its core, the ALU contains exactly this kind of binary adder circuit — scaled up to handle 32-bit or 64-bit numbers. Every time you run a Python statement like x = a + b, the CPU's ALU is executing millions of these individual gate operations in hardware to produce the result.

Subtraction is performed using two's complement: negate the subtrahend (flip bits and add 1) and add. This means the ALU needs only an adder circuit for both addition and subtraction — a beautiful economy of design.

Frequently asked questions

Why is it called a "half" adder if it can add two bits perfectly?

It is called a half adder because it handles only half the general problem of binary column addition. A complete adder in a multi-bit circuit must also accept a carry-in from the previous column. The half adder cannot do that — it has no C_in input. Two half adders combined (with an OR gate for the carry) form a full adder that handles all three inputs.

Do I need to draw logic gate diagrams for GCSE?

It depends on your specification. AQA GCSE Computer Science expects you to understand truth tables and logic expressions, and to complete or construct simple circuits from AND, OR, NOT, and NAND gates. XOR is used to describe the half adder's sum output. You may be given the gate symbols and asked to complete a truth table from a diagram, so practise reading gate diagrams as well as constructing them.

How is subtraction done with the same adder circuit?

Subtraction uses two's complement representation. To compute A − B, the ALU negates B (flip all its bits and add 1) and then adds the result to A using the standard adder. The CPU achieves this by routing B through NOT gates and setting the initial carry-in of the adder chain to 1. This elegant trick means no separate subtraction circuit is needed — the same ripple-carry adder handles both operations.

What happens if the result of an addition is too large to fit in the available bits?

This is called integer overflow. If two 8-bit numbers are added and the result requires a 9th bit, that carry bit is lost (unless captured separately), and the stored result is wrong. For example, 11111111 (255) + 00000001 (1) = 100000000, but in 8 bits only 00000000 is stored — the carry is discarded. Hardware and programming languages deal with overflow in different ways, but the root cause is always the fixed bit-width of the adder.

Build your intuition for logic circuits from first principles — Professor Turing at aitutors.me will guide you through every gate and truth table.