The fetch-decode-execute (FDE) cycle is the repeating sequence of steps a CPU follows to process every instruction in a program. Understanding this cycle — and the registers involved at each stage — is essential for GCSE Computer Science questions on computer architecture and CPU performance.
What is the Von Neumann architecture?
The FDE cycle operates within the Von Neumann architecture, the design model used by almost all modern computers. Its key feature is the stored-program concept: both the program instructions and the data they operate on are held in the same memory (RAM) and fetched by the CPU as needed. The CPU consists of:
- ALU (Arithmetic Logic Unit) — performs arithmetic (+, −, ×, ÷) and logical operations (AND, OR, NOT, comparisons).
- Control Unit (CU) — directs the flow of data between CPU components, memory, and I/O devices. It does not process data itself; it orchestrates everything else.
- Registers — tiny, ultra-fast storage locations inside the CPU.
What registers are involved in the FDE cycle?
| Register | Full name | Purpose |
|---|---|---|
| PC | Program Counter | Holds the memory address of the next instruction to fetch |
| MAR | Memory Address Register | Holds the address being accessed in RAM (read or write) |
| MDR | Memory Data Register | Holds the data just read from RAM or about to be written |
| CIR | Current Instruction Register | Holds the instruction currently being decoded and executed |
| ACC | Accumulator | Holds the result of the most recent ALU operation |
How does the FDE cycle work step by step?
FETCH:
- The address in the PC is copied to the MAR.
- The PC is incremented by 1 (so it points to the next instruction ready for the following cycle).
- The instruction stored at the address in the MAR is fetched from RAM and placed in the MDR.
- The instruction is copied from the MDR into the CIR.
DECODE: 5. The Control Unit decodes the instruction in the CIR — it identifies the operation code (opcode) and the operand (the data or address to act upon).
EXECUTE: 6. The appropriate action is carried out:
- If it is an arithmetic/logical operation → the ALU performs it and stores the result in the ACC.
- If it is a memory read → the address goes to the MAR; the data comes back to the MDR.
- If it is a jump instruction → the PC is updated to a new address.
- The cycle immediately repeats from step 1 with the new value in the PC.
Worked trace — instruction at address 100: ADD 200 (add the value stored at address 200 to the accumulator)
| Step | Component | Action |
|---|---|---|
| 1 | PC → MAR | MAR = 100 |
| 2 | PC | PC = 101 |
| 3 | RAM → MDR | MDR = "ADD 200" |
| 4 | MDR → CIR | CIR = "ADD 200" |
| 5 | CU | Decode: opcode = ADD, operand = 200 |
| 6a | 200 → MAR | MAR = 200 |
| 6b | RAM → MDR | MDR = value at address 200 |
| 6c | ALU | ACC = ACC + MDR |
What factors affect CPU performance?
| Factor | Effect on performance |
|---|---|
| Clock speed (GHz) | More cycles per second → more FDE cycles per second. A 3 GHz CPU performs ~3 billion cycles per second. |
| Number of cores | Each core can run its own FDE cycle simultaneously. A quad-core CPU can process four instruction streams in parallel. |
| Cache size | Cache is faster memory inside the CPU. A larger cache holds more instructions/data close to the CPU, reducing the time lost waiting for RAM. |
| Word size | A wider word (e.g. 64-bit vs 32-bit) means the CPU can process more data in a single operation. |
How does cache memory improve performance?
The ALU can process data in nanoseconds, but fetching from RAM takes tens of nanoseconds — orders of magnitude slower. Cache memory (SRAM, built onto the CPU chip) stores copies of recently used or likely-to-be-needed instructions and data. Most CPUs have three levels:
- L1 cache — smallest (KB), fastest, built directly into each core.
- L2 cache — larger (MB), slightly slower, may be per-core or shared.
- L3 cache — largest (MB–tens of MB), shared across all cores, slowest of the three but still far faster than RAM.
When the CPU needs data, it checks L1 first, then L2, then L3, then RAM. A cache hit (data found in cache) is much faster than a cache miss (must go to RAM).
Frequently asked questions
Why does the PC increment during the Fetch stage rather than after Execute?
The PC is incremented during Fetch so that it immediately points to the next instruction — even while the current instruction is still being decoded and executed. In pipelined CPUs, the next instruction can begin being fetched while the current one is still being decoded. Incrementing during Fetch makes this overlap possible and keeps the PC always one step ahead.
What happens to the FDE cycle when there is a jump instruction?
A jump instruction overrides the PC with a new address rather than the auto-incremented one. An unconditional jump (like GOTO 500) immediately sets PC = 500 so the next fetch starts there. A conditional jump (like IF ACC = 0 THEN GOTO 500) only updates the PC if the condition is true; otherwise the incremented PC stands and execution continues sequentially.
What is the difference between the MDR and the MAR?
The MAR (Memory Address Register) holds an address — a location number in RAM. The MDR (Memory Data Register) holds the data that was read from or is about to be written to that address. Think of it like a library: the MAR is the shelf number you tell a librarian, and the MDR is the book they bring back to you.
How does clock speed differ from the number of cores?
Clock speed (in GHz) determines how many FDE cycles a single core can perform per second. More cores mean more separate FDE pipelines running simultaneously. A 4-core CPU at 2 GHz may outperform a 1-core CPU at 3 GHz on tasks that can be split across cores (like video encoding), but for a single sequential task, the higher clock speed wins. Most real-world workloads benefit from both higher clock speed and more cores.
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