An interrupt is a signal sent to the CPU that tells it to pause its current task and deal with a higher-priority event. Without interrupts, a CPU would constantly check every device to see whether it needed attention — enormously wasteful. Interrupts let the processor focus on useful work and respond to events only when they occur.
Why does the CPU need interrupts?
Imagine you are writing an essay and your phone rings. You do not scan your phone every second to see whether it is ringing; instead, it interrupts you. You pause the essay, handle the call, then return to exactly where you left off.
A CPU faces the same challenge. Hundreds of devices — keyboards, network cards, storage drives, timers — all need to communicate with the processor at unpredictable moments. Polling (constantly checking each device in turn) wastes processor time and slows everything down. Interrupts solve this: a device signals the CPU only when it actually has something to report, and the CPU responds immediately.
What types of interrupts exist?
| Type | Source | Example |
|---|---|---|
| Hardware interrupt | External device | Key pressed on keyboard; network packet arrives |
| Software interrupt | Running program | Program requests an OS service (e.g. write to disk) |
| Timer interrupt | Internal clock | Operating system regains control every few milliseconds |
| Fault/exception | CPU detects error | Division by zero; invalid memory access |
Hardware and timer interrupts are the most commonly examined at GCSE level.
What happens when an interrupt arrives?
The CPU does not abandon its current task immediately and at random. It checks for pending interrupts at the end of each fetch-decode-execute cycle. If an interrupt is flagged, the following sequence occurs:
- Finish the current instruction (the CPU does not stop mid-instruction).
- Save the current state — the contents of all registers (including the program counter) are copied to a reserved area of memory called the stack. This is essential so the original task can be resumed exactly.
- Load the interrupt service routine (ISR) — the program counter is updated to point to the start of the ISR for this interrupt type.
- Execute the ISR — the CPU runs the ISR code, which handles the event (e.g. reads the key that was pressed and stores the character in a buffer).
- Restore the saved state — the original register values are popped back off the stack.
- Resume the original task from the exact instruction where it was paused.
What is an interrupt service routine (ISR)?
An interrupt service routine (also called an interrupt handler) is a short program stored in memory that the CPU runs in response to a specific interrupt. Every type of interrupt has its own ISR. The location of each ISR is stored in a table called the interrupt vector table.
ISRs must be short and fast: they run with interrupts temporarily disabled to prevent one ISR from being interrupted by another. A slow ISR can make the whole system feel sluggish — this is why device drivers (which often contain ISRs) are written in low-level, highly optimised code.
How are interrupts prioritised?
Multiple interrupts can arrive simultaneously. The CPU resolves this using a priority system: each interrupt is assigned a priority level, and higher-priority interrupts are handled first.
Example priority ordering (high to low):
| Priority | Interrupt type | Reason |
|---|---|---|
| 1 (highest) | Hardware fault / power failure | Must be dealt with immediately or data is lost |
| 2 | Timer interrupt | Operating system must regain CPU control regularly |
| 3 | Keyboard / mouse | User expects responsive input |
| 4 (lowest) | Network packet received | Can wait briefly without the user noticing |
A low-priority ISR can itself be interrupted by a higher-priority interrupt. The processor saves the ISR's state and handles the more urgent event first — effectively nesting interrupts.
How do interrupts enable multi-tasking?
Modern operating systems use a timer interrupt to implement multi-tasking. The system timer fires several hundred times per second. Each time it fires, the OS regains control of the CPU, saves the current program's state, and switches to the next program in the queue. This switching is called a context switch.
Each program appears to run continuously from the user's perspective, but in reality the CPU is slicing its time among many programs. This technique is called time-slicing or pre-emptive multi-tasking. Interrupts are the mechanism that makes it possible — without them, a program could monopolise the CPU indefinitely.
Frequently asked questions
Do I need to know the interrupt vector table for GCSE?
At GCSE level, you need to know that different interrupt types are handled by different ISRs, and that the CPU knows which ISR to call because the addresses are stored in a table. You do not need to describe the internal structure of the interrupt vector table in detail. The key concept is that the CPU does not contain the ISR code itself — it simply has a reference to where each ISR lives in memory.
What is the difference between a hardware interrupt and a software interrupt?
A hardware interrupt is generated by a physical device outside the CPU — a key being pressed, a disk read completing, or a network packet arriving. A software interrupt is generated by a running program, typically to request a service from the operating system such as reading a file or allocating memory. Both result in the CPU saving its state, running an ISR, and then resuming, but their sources and priorities differ.
Why does the CPU save its state to a stack rather than any other memory location?
The stack is a last-in-first-out structure, which perfectly matches the behaviour needed for nested interrupts. If interrupt A is interrupted by higher-priority interrupt B, the state is pushed twice. When B's ISR finishes, B's state is popped first (restoring the middle of interrupt A's ISR); when A's ISR finishes, A's state is popped (restoring the original program). A fixed memory location could only hold one saved state at a time.
Can an interrupt arrive while the CPU is already handling another interrupt?
Yes, but it depends on whether interrupts are enabled or disabled at that moment. Most processors disable further interrupts when they begin executing an ISR, to prevent confusion. When the ISR completes, interrupts are re-enabled. More sophisticated systems allow higher-priority interrupts to interrupt lower-priority ISRs, creating a nested structure — but the stack always lets the CPU unwind back through every level in the correct order.
Professor Turing can walk you through the interrupt cycle — and every CPU architecture topic — with Socratic questions and diagrams at aitutors.me.